JK FLIP-FLOP

JK FLIP-FLOP
Using a clock pulse to control the change of state of the flip-flop synchronizes its operation with the rest of th circuit.this avoids the “race condition” that can occur with the RS flip-flop. The device is triggered by the negative(falling) edge of yhe clock pulse.

LOGIC SYMBOL:
JK FLIP-FLOP SYMBOL
Circuit diagram
CIRCUIT DIAGRAM JK FLIP-FLOP

TRUTH TABLE
J
K
Qn-1
ACTION
0
0
Qn
(no change)
0
1
0
Reset
1
0
1
Set
1
1
Qn
toggle


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